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low skew, 1-to-5, differential-to- 3.3v lvpecl fanout buffer ics85304-01 idt? / ics? 3.3v lvpecl fanout buffer 1 ics85304ag-01 rev. e july 8, 2008 general description the ics85304-01 is a low skew, high performance 1-to-5 differential-to-3.3v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the ics85304-01 has two selectable clock inputs. the clkx, nclkx pairs can accept most standard differential input levels. the clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics85304-01 ideal for those applications demanding well defined performance and repeatability. features ? five 3.3v differenti al lvpecl output pairs ? selectable differential clkx/nclkx input pairs ? clkx/nclkx input pairs can accept the following differential levels: lvds, lvpecl, lvhstl, sstl and hcsl levels ? maximum output frequency: 650mhz ? translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on nclkx inputs ? output skew: 35ps (maximum) ? part-to-part skew: 150ps (maximum) ? propagation delay: 2.1ns (maximum) ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 0 1 d q le 0 1 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 clk_en clk0 nclk0 clk_sel pulldown pullup pullup pulldown clk1 nclk1 pullup pulldown 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 q4 nq3 q3 nq2 q2 nq1 q1 nq0 q0 nq4 v cc clk_en v cc nclk1 clk1 v ee nclk0 clk0 clk_sel v cc pin assignment ics85304-01 20-lead tssop 6.5mm x 4.4mm x 0.925mm package body g package top view block diagram
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 2 ics85304ag-01 rev. e july 8, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q0, nq0 output differential output pair. lvpecl interface levels. 3, 4 q1, nq1 output differential output pair. lvpecl interface levels. 5, 6 q2, nq2 output differential output pair. lvpecl interface levels. 7, 8 q3, nq3 output differential output pair. lvpecl interface levels. 9, 10 q4, nq4 output differential output pair. lvpecl interface levels. 11, 18, 20 v cc power positive supply pins. 12 clk_sel input pulldown clock select input. when high, sele cts clk1, nclk1 inputs. when low, selects clk0, nclk0 inputs. lvttl/lvcmos interface levels. 13 clk0 input pulldown non-inverting differential clock input. 14 nclk0 input pullup inverting differential clock input. 15 v ee power negative supply pin. 16 clk1 input pulldown non-inverting differential clock input. 17 nclk1 input pullup inverting differential clock input. 19 clk_en input pullup synchronizing clock enable. when high, clock outputs follow clock input. when low, qx outputs are forced lo w, nqx outputs are forced high. lvttl/lvcmos interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ?
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 3 ics85304ag-01 rev. e july 8, 2008 function tables table 3a. control input function table after clk_en switches, the clock outputs are disabled or enab led following a rising and falling input clock edge as shown in fi gure 1. in the active mode, the state of the outputs are a func tion of the clkx/nclkx inputs as described in table 3b. figure 1. clk_en timing diagram table 3b. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. inputs outputs clk_en clk_sel selected source q0:q4 nq0:nq4 0 0 clk0, nclk0 disabled; low disabled; high 0 1 clk1, nclk1 disabled; low disabled; high 1 0 clk0, nclk0 enabled enabled 1 1 clk1, nclk1 enabled enabled inputs outputs input to output mode polarity clk0 or clk1 nclk0 or nclk1 q[0:4] nq[0:4] 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-ended to differential non-inverting 1 biased; note 1 high low single-ended to differential non-inverting biased; note 1 0 high low single-ended to differential inverting biased; note 1 1 low high single-ended to differential inverting enabled disabled clk[0:1] clk_en nclk[0:1] q[0:4] nq[0:4]
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 4 ics85304ag-01 rev. e july 8, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, v ee =0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = 3.3v 5%, v ee =0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ja 73.2c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v i ee power supply current 55 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 3.765 v v il input low voltage -0.3 0.8 v i ih input high current clk_en v cc = v in = 3.465v 5 a clk_sel v cc = v in = 3.465v 150 a i il input low current clk_en v cc = 3.465v, v in = 0v -150 a clk_sel v cc = 3.465v, v in = 0v -5 a
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 5 ics85304ag-01 rev. e july 8, 2008 table 4c. differential dc characteristics, v cc = 3.3v 5%, v ee =0v, t a = -40c to 85c note 1: v il should not be less than -0.3v note 2: common mode input voltage is defined as v ih . table 4d. lvpecl dc characteristics, v cc = 3.3v 5%, v ee =0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v. ac electrical characteristics table 5. ac characteristics, v cc = 3.3v 5%, v ee =0v, t a = -40c to 85c all parameters measured at 500mhz unless noted otherwise the cycle-to-cycle jitter on the input will equal the jitte r on the output. the pa rt does not add jitter. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output diffe rential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the output s are measured at the differential cross points. symbol parameter test conditio ns minimum typical maximum units i ih input high current nclk0, nclk1 v cc = v in = 3.465v 5 a clk0, clk1 v cc = v in = 3.465v 150 a i il input low current nclk0, nclk1 v cc = 3.465v, v in = 0v -150 a clk0, clk1 v cc = 3.465v, v in = 0v -5 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc ? 0.85 v symbol parameter test conditio ns minimum typical maximum units v oh output high current; note 1 v cc ? 1.4 v cc ? 1.0 a v ol output low current; note 1 v cc ? 2.0 v cc ? 1.7 a v swing peak-to-peak output voltage swing 0.6 0.85 v parameter symbol test conditio ns minimum typical maximum units f max maximum output frequency 650 mhz t pd propagation delay; note 1 ? 650mhz 1.0 2.1 ns t sk(o) output skew; note 2, 3 35 ps t sk(pp) part-to-part skew; note 3, 4 150 ps t r / t f output rise/fall time 20% to 80% @ 50mhz 300 700 ps odc output duty cycle 48 50 52 %
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 6 ics85304ag-01 rev. e july 8, 2008 parameter measureme nt information 3.3v output load ac test circuit output skew output duty cycle/pulse width/period differential input level part-to-part skew output duty cycle/pulse width/period - scope qx nqx lvpecl v ee v cc 2v% 1.3v 0.165v - t sk(o) nqx qx nqy qy t pd nq[0:4] q[0:4] nclk0, clk0, nclk1 clk1 v cc v ee nclk0, nclk1 clk0, clk1 v cmr cross points v pp t sk(pp) part 1 part 2 nqx qx nqy qy nq[0:4] q[0:4] t pw t period t pw t period odc = x 100%
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 7 ics85304ag-01 rev. e july 8, 2008 parameter measurement in formation, continued output rise/fall time application information wiring the differential input to accept single-ended levels figure 1 shows how the differential input can be wired to accept single-ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ende d signal driving differential input 20% 80% 80% 20% t r t f v swing nq[0:4] q[0:4] v_ref single ended clock input v cc clkx nclkx r1 1k c1 0.1u r2 1k
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 8 ics85304ag-01 rev. e july 8, 2008 differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 2c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 2b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 2f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 9 ics85304ag-01 rev. e july 8, 2008 recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 10 ics85304ag-01 rev. e july 8, 2008 power considerations this section provides information on power dissipa tion and junction temperature for the ics85304-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85304-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 55ma = 190.57mw power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 5 * 30.2mw = 151mw total power_ max (3.465v, with all outputs s witching) = 190.57mw + 151mw = 341.57mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 73.2c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 70c + 0.342w * 73.2c/w = 95c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ja for 20 lead tssop, forced convection ja by velocity linear feet per minute 0 200 500 single-layer pcb, jedec standard te st boards 114.5c/ w 98.0c/w 88.0c/w multi-layer pcb, jedec standard te st boards 73.2c/w 6 6.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards . the data in the second row pertains to most designs.
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 11 ics85304ag-01 rev. e july 8, 2008 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 4. figure 4. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 1.0v (v cc_max ? v oh_max ) = 1.0v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 1.0v)/50 ? ] * 1.0v = 20mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw v out v cc v cc - 2v q1 rl 50
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 12 ics85304ag-01 rev. e july 8, 2008 reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics85304-01 is: 489 package outline and package dimensions package outline - g suffix for 20 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity linear feet per minute 0 200 500 single-layer pcb, jedec standard te st boards 114.5c/ w 98.0c/w 88.0c/w multi-layer pcb, jedec standard te st boards 73.2c/w 6 6.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards . the data in the second row pertains to most designs. all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 13 ics85304ag-01 rev. e july 8, 2008 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 85304ag-01 ics85304ag01 20 lead tssop tube 0 c to 70 c 85304AG-01T ics85304ag01 20 lead tssop 2500 tape & reel 0 c to 70 c 85304ag-01lf ics85304a01l ?lead-free? 20 lead tssop tube 0 c to 70 c 85304ag-01lft ics85304a01l ?lead-free? 20 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserv es the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics85304-01 low skew, 1-to-5 differential- to- 3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 14 ics85304ag-01 rev. e july 8, 2008 revision history sheet rev table page description of change date a t4b t4d t5 4 5 5 v cmr values changed from 1.5v min. to 0.5v min.; v dd max. to v cc - 0.85v max. v oh values changed from 1.9a min. to v cc - 1.4a min.; 2.3a max. to v cc - 1.0a. v ol values changed from 1.2a min. to v cc - 2.0a; 1.6a max. to v cc - 1.7a max. replaced tp lh and tp hl with t pd at the same values. replaced t pw and values of t cycle /2 - 40 min., t cycle /2 typ., t cycle /2 + 40 max. with odc at values of 48% min., 50% typ., 52% max. 5/14/01 b t4d t5 5 lvpecl dc characteristics table - added i ih , i il , v pp , and v cmr rows. ac characteristics table - t r and t f values changed from 275ps min to 300ps min; 650ps max. to 700ps max. 5/22/01 c t4d 5 differential dc characteristics table - v cmr values changed from v cc - 0.85v max. to v cc. 8/21/01 c 3 revised figure 1, clk_en timing diagram. 10/17/01 c 3 revised figure 1, clk_en timing diagram. 11/2/01 c t3b 3 revised inputs heading from clk or clk, npclk or npclk to clk or pclk, nclk or npclk. 12/28/01 c 8 added termination for lvepcl output section. 5/30/02 c 6 7 3.3v output load test circuit diagram - corrected v ee = -1.3v 0.135v to v ee = -1.3v 0.165v. updated output rise/fall time diagram. 8/26/02 d t2 t9 1 2 4 6 8 9 14 added lead-free bullet in features section. pin characteristics table - changed c in 4pf max. to 4pf typical. absolute maximum ratings, updated outputs rating. updated parameter measurement information. added differential clock input interface section. added lvpecl clock input interface section. ordering information table - added lead free part number. 6/17/04 e t9 8 9 10 13 per document errata, nen-08-03, corrected name of pclk/npclk to clk1/nclk1 and changed clk/nclk to clk0/nclk0 throughout the datasheet. updated differential clock input interface section. deleted lvpecl clock input interface section. added recommendations for unused input and output pins section. power considerations - corrected junction temperature calculations. ordering information t able - corrected marking. updated format throughout the datasheet. 6/20/08 e 3 corrected figure 1, clk_en timing diagram. 7/8/08
ics85304-01 low skew, 1-to-5 differential-t o- 3.3v lvpecl fanout buffer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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